The present invention relates to a diagnostic system for a data processor constructed so that during its normal operation the output of a memory is input directly to a combinational circuit, such as an arithmetic unit or the like, and the output of the combinational circuit is input directly to the memory. More particularly, the invention pertains to a diagnostic system which diagnoses a circuit referring to a memory via an internal register.
FIG. 1 is a block diagram showing the principles of a conventional logic unit. Reference, numerals 1-A to 1-C indicate gates; 2 designates a memory; 3 identifies a register; SDi denotes scan-in data; SDo represents scan-out data; X shows input data to the gate 1-A; and Y refers to output data from the gate 1-C. Incidentally, the gates 1-A to 1-C are not mere gates but are combinational circuits, such as arithmetic circuits or the like. The combinational circuit is diagnosed by checking its input and output data.
The output data from the gate 1-A is input directly to the memory 2 and the input data to the gate 1-B is data read out directly from the memory 2. In general, however, a scan function for the memory 2 is not provided; therefore, in the arrangement of FIG. -, the gates 1-A and 1-B cannot be diagnosed individually.
FIG. 2 is a block diagram showing the principles of another conventional logic unit which is provided with a write data register 4 and a read data register 5 in addition to the arrangement of FIG. 1. In the case of diagnosing the gate 1-A, the input data X is provided thereto and its output is set in the write data register 4, after which data of the write data register 4 is read out therefrom by a serial scan operation. In the case of diagnosing the gate 1-B, data is written by a serial scan operation into the read data register 5 and its output data is input to the gate 1-B, the output data of which is set in the register 3. Then the data of the register 3 is read out therefrom by the serial scan operation. In this way, the gates 1-A and 1-B can be diagnosed. The write data register 4 and the read data register 5 are used during the diagnosis only and, during normal operation, for speeding up the operation of the logic unit, they are by-passed so that the output data of the gate 1-A is input directly to the memory 2 and the read data of the memory 2 is input directly to the gate 1-B.
Since the provision of the registers which are used solely for diagnosis increases the amount of hardware used, it has been proposed to employ existing registers as the aforesaid read and write data registers 4 and 5.
Incidentally, in the case where a desired test pattern is set in an instruction register, the diagnostic ratio is lowered unless an operation according to the test pattern is not performed normally. In the absence of a scan function for a memory, even if an instruction for reference to the memory, for instance, an instruction for adding data of first and second memories and for storing the added data in the first memory, indicated by (MEM 1).rarw.(MEM 1)+(MEM 2), is provided to an instruction register, the diagnostic results cannot be taken out to the exterior. Therefore, when an instruction of the memory reference format is given, no diagnosis is possible. Accordingly, a high proportion of the memory reference instructions present a serious obstacle to diagnosis